A motor has been used as the driving source in a power steering apparatus or in an industrial robot, etc. Such an apparatus has often performed PWM control to accurately control the output torque of the motor (for example, Patent Publication No. sho 60-131093).
FIG. 7 is an example of the motor driving circuit used in a conventional electrical power steering, in which the circuit is connected to a microcomputer (not shown) to control it. That is, as show in in FIG. 7, OP 0 to 9 and IP 2 are the input and output ports of the microcomputer, respectively. OP 0 to 7 output the data indicating the on duty of a PWM control (below referred to as a PWM data), and OP 8 and 9 output the control signals (below referred to as a direction control signal) for controlling the forward and reverse rotations of motor 8. Herein, PWM data is the data of 1 to 100 given by a binary number. The direction control signal is output as a high level at OP 8 during forward rotation, as a low level at OP 9 during reverse rotation and as a low level at both ports during the disconnection of the power source from the motor.
PWM data is supplied to PWM unit 210. PWM unit 210 comprises register 211 for storing PWM data, clock CLK for generating the clock pulse of 1.5 MHz, 100 binary counter 212 for counting the clock pulse, comparator 213 for comparing the counting data of counter 212 with PWM data, which register 211 stores therein, and AND gate AN3. Counter 212 counts the value of 1 to 99, repeatedly. Comparator 213 outputs the high level when the counting data is less than the PWM data and the low level when the counting data is more than the PWM data. Therefore, a PWM signal of 15 MHz with the high level being continued between the on duties is generated.
The PWM signal is input to one input terminal of AND gate AN3 which has two input terminals. The other input terminal of AND gate AN3 receives a current limiting signal from current limiting unit 230, but it is now assumed that this signal is at a high level.
The output of PWM unit 210, for example, the output of AND gate AND3 (below referred to as the current controlling signal), is applied one input terminal of each of the AND gates AN1 and AN2. The other input terminal of AND gate AN1 is connected to output port OP8, and the other input terminal of AND gate AN2 is connected to output port OP9. That is to say, when the direction control signal from OP8 is at a high level, the current control signal is output from AND gate AN1. When OP9 outputs the high level, the current control signal is output from AND gate AN2.
The output from AND gate AN1 is applied to FET driver 222 and the output of AND gate AN2 is applied to FET driver 224. FET driver 222 turns on FET T2 when a high level is applied thereto. FET driver 224 turns on FET T4 when a high level is applied thereto.
On the other hand, FET driver 221 for driving FET T1 is connected to output port OP8, and FET driver 223 for driving FET T3 is connected to output port OP9, FET driver 221 turns on FET T3 when a high level is applied thereto, and FET driver 223 turns on FET T3 when a high level is applied thereto. That is, when the direction control signal from OP8 is at the high level, FET T1 is turned on, and only when the current control signal is at a high level, is FET T2 turned on, so that a current proportional to the current control signal is applied to motor 8 to cause forward rotation thereof. When the direction control signal from OP9 is at a high level, FET T3 is turned on, and only when the current control signal is at a high level does FET T4 turn on, so that the current proportional to the current control signal is supplied to motor 8 for generating the reverse rotation thereof.
Motor energizing current IM is detected as the voltage of both ends of shunt resister R by means of current limiting unit 230. This voltage is amplified by a linear amplifier including operation amplifier 231, which is the important component, after the surge is removed and is supplied to each of the comparators including operation amplifier 232 (below referred to as the load limiting comparator) and the comparator including operation amplifier 231 (below referred to as the driving prohibiting comparator). These comparators have the hysterisis characteristics. The former performs a comparison of the load limiting voltage V1, and the latter executes a comparison of driving prohibiting voltage V2 which is higher than the load limiting voltage V1. That is, if motor energization current IM exceeds the load limiting value (the current value corresponding to V1), the output of the driving prohibiting comparator is converted into a low level (and the output of the driving prohibiting comparator is applied to input port IP2 to be used for other controls, a description of the other controls is omitted herein).
The output of the load limiting comparator is supplied to AND gate AN3 of PWM unit 210 and is changed into the low level, so that the PWM signal is hindered at AND gate AN3. In other words, when even at the on duty of PWM signal motor energizing current IM is increased by the lock of motor 8, etc., and exceeds the load limiting value motor 8 is deenergized by a force to protect each of the structured elements.
This will be described below in detail with reference to the wave form of each portion as indicated in FIG. 8, When at the on duty of PWM signal flowing through the line the overload of motor 8 occurs, motor energizing current IM is increased, and the potential at point b is increased. If this potential is over load limiting voltage V1, the output of the load limiting comparator, that is, the level at point c is converted into the low level, and the output of AND gate AN3, that is, the current limiting signal passing through point d is made to be at a low level. Thus, FET driver 222 or 224 turns off FET T1 or T2, so that motor energizing current IM is cut off and the potential at point b begins to decrease. When the potential at point b decreases to below the lower value by the predetermined value .alpha. defined by the hysterisis characteristics of the load limiting comparator than load limiting voltage V1, the output of the load limiting comparator is changed into the high level.
Then, if the on duty during the overload condition of motor 8 is continued, the load limiting comparator converts it's output into the high level, and the current limiting signal passing through the point b is returned to the high level, at that time motor energizing current IM is again increased to an oscillating condition, immediately, and this motor driving circuit forces the on/off of the motor to be repeated, the speed depending upon the responsive speed of current limiting unit 230.
Generally, the responsive speed of current limiting unit 230 is set at a high speed in view of the protection of each of the components structured (if slowed, the components are not protected due to the overshoot of the current). Due to this overload condition of motor 8, it's on/off frequency is made to have a Very high value (FIG. 8 schematically represents the Wave form).
On the other hand, PWM signal is set at the optimum frequency considering the responsive characteristics of each component forming the motor driving circuit, so that the on duty is chopped at the high speed to cause the switching loss of the switch element or the increase of the radiating noise.